gd32e23x_pmu.c 8.6 KB

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  1. /*!
  2. \file gd32e23x_pmu.c
  3. \brief PMU driver
  4. \version 2019-02-19, V1.0.0, firmware for GD32E23x
  5. \version 2019-05-06, V1.0.1, firmware for GD32E23x
  6. \version 2020-11-25, V1.0.2, firmware for GD32E23x
  7. \version 2020-12-12, V1.1.0, firmware for GD32E23x
  8. \version 2021-03-30, V1.1.1, firmware for GD32E23x
  9. */
  10. /*
  11. Copyright (c) 2021, GigaDevice Semiconductor Inc.
  12. Redistribution and use in source and binary forms, with or without modification,
  13. are permitted provided that the following conditions are met:
  14. 1. Redistributions of source code must retain the above copyright notice, this
  15. list of conditions and the following disclaimer.
  16. 2. Redistributions in binary form must reproduce the above copyright notice,
  17. this list of conditions and the following disclaimer in the documentation
  18. and/or other materials provided with the distribution.
  19. 3. Neither the name of the copyright holder nor the names of its contributors
  20. may be used to endorse or promote products derived from this software without
  21. specific prior written permission.
  22. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  26. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  28. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  29. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  31. OF SUCH DAMAGE.
  32. */
  33. #include "gd32e23x_pmu.h"
  34. /*!
  35. \brief reset PMU register
  36. \param[in] none
  37. \param[out] none
  38. \retval none
  39. */
  40. void pmu_deinit(void)
  41. {
  42. /* reset PMU */
  43. rcu_periph_reset_enable(RCU_PMURST);
  44. rcu_periph_reset_disable(RCU_PMURST);
  45. }
  46. /*!
  47. \brief select low voltage detector threshold
  48. \param[in] lvdt_n:
  49. only one parameter can be selected which is shown as below:
  50. \arg PMU_LVDT_0: voltage threshold is 2.1V
  51. \arg PMU_LVDT_1: voltage threshold is 2.3V
  52. \arg PMU_LVDT_2: voltage threshold is 2.4V
  53. \arg PMU_LVDT_3: voltage threshold is 2.6V
  54. \arg PMU_LVDT_4: voltage threshold is 2.7V
  55. \arg PMU_LVDT_5: voltage threshold is 2.9V
  56. \arg PMU_LVDT_6: voltage threshold is 3.0V
  57. \arg PMU_LVDT_7: voltage threshold is 3.1V
  58. \param[out] none
  59. \retval none
  60. */
  61. void pmu_lvd_select(uint32_t lvdt_n)
  62. {
  63. /* disable LVD */
  64. PMU_CTL &= ~PMU_CTL_LVDEN;
  65. /* clear LVDT bits */
  66. PMU_CTL &= ~PMU_CTL_LVDT;
  67. /* set LVDT bits according to lvdt_n */
  68. PMU_CTL |= lvdt_n;
  69. /* enable LVD */
  70. PMU_CTL |= PMU_CTL_LVDEN;
  71. }
  72. /*!
  73. \brief select LDO output voltage
  74. these bits set by software when the main PLL closed
  75. \param[in] ldo_output:
  76. only one parameter can be selected which is shown as below:
  77. \arg PMU_LDOVS_LOW: LDO output voltage low mode
  78. \arg PMU_LDOVS_HIGH: LDO output voltage high mode
  79. \param[out] none
  80. \retval none
  81. */
  82. void pmu_ldo_output_select(uint32_t ldo_output)
  83. {
  84. PMU_CTL &= ~PMU_CTL_LDOVS;
  85. PMU_CTL |= ldo_output;
  86. }
  87. /*!
  88. \brief disable PMU lvd
  89. \param[in] none
  90. \param[out] none
  91. \retval none
  92. */
  93. void pmu_lvd_disable(void)
  94. {
  95. /* disable LVD */
  96. PMU_CTL &= ~PMU_CTL_LVDEN;
  97. }
  98. /*!
  99. \brief PMU work at sleep mode
  100. \param[in] sleepmodecmd:
  101. only one parameter can be selected which is shown as below:
  102. \arg WFI_CMD: use WFI command
  103. \arg WFE_CMD: use WFE command
  104. \param[out] none
  105. \retval none
  106. */
  107. void pmu_to_sleepmode(uint8_t sleepmodecmd)
  108. {
  109. /* clear sleepdeep bit of Cortex-M23 system control register */
  110. SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  111. /* select WFI or WFE command to enter sleep mode */
  112. if(WFI_CMD == sleepmodecmd){
  113. __WFI();
  114. }else{
  115. __WFE();
  116. }
  117. }
  118. /*!
  119. \brief PMU work at deepsleep mode
  120. \param[in] ldo:
  121. only one parameter can be selected which is shown as below:
  122. \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
  123. \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
  124. \param[in] deepsleepmodecmd:
  125. only one parameter can be selected which is shown as below:
  126. \arg WFI_CMD: use WFI command
  127. \arg WFE_CMD: use WFE command
  128. \param[out] none
  129. \retval none
  130. */
  131. void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
  132. {
  133. /* clear stbmod and ldolp bits */
  134. PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
  135. /* set ldolp bit according to pmu_ldo */
  136. PMU_CTL |= ldo;
  137. /* set sleepdeep bit of Cortex-M23 system control register */
  138. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  139. /* select WFI or WFE command to enter deepsleep mode */
  140. if(WFI_CMD == deepsleepmodecmd){
  141. __WFI();
  142. }else{
  143. __SEV();
  144. __WFE();
  145. __WFE();
  146. }
  147. /* reset sleepdeep bit of Cortex-M23 system control register */
  148. SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  149. }
  150. /*!
  151. \brief pmu work at standby mode
  152. \param[in] none
  153. \param[out] none
  154. \retval none
  155. */
  156. void pmu_to_standbymode(void)
  157. {
  158. /* switch to IRC8M clock as system clock, close HXTAL */
  159. RCU_CFG0 &= ~RCU_CFG0_SCS;
  160. RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
  161. /* set stbmod bit */
  162. PMU_CTL |= PMU_CTL_STBMOD;
  163. /* reset wakeup flag */
  164. PMU_CTL |= PMU_CTL_WURST;
  165. /* set sleepdeep bit of Cortex-M23 system control register */
  166. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  167. REG32( 0xE000E010U ) &= 0x00010004U;
  168. REG32( 0xE000E180U ) = 0XFFFFFFFBU;
  169. REG32( 0xE000E184U ) = 0XFFFFFFFFU;
  170. REG32( 0xE000E188U ) = 0xFFFFFFFFU;
  171. /* select WFI command to enter standby mode */
  172. __WFI();
  173. }
  174. /*!
  175. \brief enable wakeup pin
  176. \param[in] wakeup_pin:
  177. one or more parameters can be selected which are shown as below:
  178. \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
  179. \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13), only supported in GD32E230 devices
  180. \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
  181. \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
  182. \param[out] none
  183. \retval none
  184. */
  185. void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
  186. {
  187. PMU_CS |= wakeup_pin;
  188. }
  189. /*!
  190. \brief disable wakeup pin
  191. \param[in] wakeup_pin:
  192. one or more parameters can be selected which are shown as below:
  193. \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
  194. \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13), only supported in GD32E230 devices
  195. \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
  196. \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
  197. \param[out] none
  198. \retval none
  199. */
  200. void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
  201. {
  202. PMU_CS &= ~(wakeup_pin);
  203. }
  204. /*!
  205. \brief enable backup domain write
  206. \param[in] none
  207. \param[out] none
  208. \retval none
  209. */
  210. void pmu_backup_write_enable(void)
  211. {
  212. PMU_CTL |= PMU_CTL_BKPWEN;
  213. }
  214. /*!
  215. \brief disable backup domain write
  216. \param[in] none
  217. \param[out] none
  218. \retval none
  219. */
  220. void pmu_backup_write_disable(void)
  221. {
  222. PMU_CTL &= ~PMU_CTL_BKPWEN;
  223. }
  224. /*!
  225. \brief get flag state
  226. \param[in] flag:
  227. only one parameter can be selected which is shown as below:
  228. \arg PMU_FLAG_WAKEUP: wakeup flag
  229. \arg PMU_FLAG_STANDBY: standby flag
  230. \arg PMU_FLAG_LVD: lvd flag
  231. \param[out] none
  232. \retval FlagStatus SET or RESET
  233. */
  234. FlagStatus pmu_flag_get(uint32_t flag)
  235. {
  236. FlagStatus ret_status = RESET;
  237. if(PMU_CS & flag){
  238. ret_status = SET;
  239. }
  240. return ret_status;
  241. }
  242. /*!
  243. \brief clear flag bit
  244. \param[in] flag:
  245. one or more parameters can be selected which are shown as below:
  246. \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
  247. \arg PMU_FLAG_RESET_STANDBY: reset standby flag
  248. \param[out] none
  249. \retval none
  250. */
  251. void pmu_flag_clear(uint32_t flag)
  252. {
  253. if(RESET != (flag & PMU_FLAG_RESET_WAKEUP)){
  254. /* reset wakeup flag */
  255. PMU_CTL |= PMU_CTL_WURST;
  256. }
  257. if(RESET != (flag & PMU_FLAG_RESET_STANDBY)){
  258. /* reset standby flag */
  259. PMU_CTL |= PMU_CTL_STBRST;
  260. }
  261. }